This invention relates to a semiconductor memory device used as a RAM mainly in a CMOS integrated circuit device, etc., and more particularly to a semiconductor memory device having a reduced mask pattern area and free from an erroneous operation at the time of read operation.
A typical circuit example of a conventional semiconductor RAM and its timing chart are shown in FIGS. 1 and 2, respectively. As shown, data write operation from a data line 5 to a holding circuit 2 and data read operation from the holding circuit 2 to the data line 5 are conducted through a transmission gate 1 comprised of an N-type MOS transistor 1a and a P-type MOS transistor 1b. This transmission gate 1 is controlled by a control circuit 4 on the basis of a write clock .phi. W and a read clock .phi. R delivered thereto. In that case, the conventional circuit is constructed to allow both the N-type MOS transistor 1a and the P-type MOS transistor 1b constituting the transmission gate 1 to be turned on both at the time of write operation and at the time of read operation.
In the circuit shown in FIG. 1, a stray capacitor 5a exists on the data line 5 in associated therewith and the data holding circuit 2 has a capacitor 2a therein. In the case of reading out, from the holding circuit 2, a potential different from a potential stored in the stray capacitor 5a of the data line 5, charge transfer takes place between the stray capacitor 5a of the data line 5 and the capacitor 2a of the data holding circuit 2 immediately after the transmission gate 1 is turned on, so that a hold potential of the holding circuit 2 changes. If the circuit is not suitably designed, such a hold potential may vary to much degree to exceed above a threshold voltage V.sub.TH of the holding circuit. Thus, as shown in FIG. 3, the data held in the holding circuit 2 may change to a different value.
For a measure therefor, a method is adopted to suppress the value of the stray capacitor 5a of the data line 5 so that it is equal to a small value, or to allow the capacitor 2a of the holding circuit 2 to have a large value, thereby to hold down a change in a hold potential of the holding circuit 2 to a small value so that it does not exceed above a threshold value V.sub.TH, thus to prevent data held from being changed.
However, with this method, the restriction on the mask pattern would be increased and the area of the mask pattern would be also increased. Particularly in a RAM including a large number of data holding circuits 2, such an influence would be conspicuously exhibited.